Morse talks about how he ended up at Intel his interest in Volkswagens helped , his freedom to innovate at what was otherwise a buttoned-down company, and the importance of a brand-new style of chip development--as well as the feature that he called SEX. SM: I was always fascinated by electricity, as far back as I can remember.
I recall in sixth grade taking out whatever books I could find in the library on the topic. In junior high I asked my mother what field could I go into that would combine my love of electricity with my strong ability in mathematics.
From then on my career course was charted, and I never deviated--I went on to get a bachelor's, a master's, and a PhD, all in electrical engineering. SM: Computer courses were unheard of when I did my undergraduate work, and even in graduate school the only exposure that I had to programming was an after-hours noncredit course on Fortran.
At the conclusion of that course, we were allowed to run just one program on the school's IBM Of course we didn't run it ourselves--we punched the program onto a deck of cards and handed the deck to a computer operator. We never even got to see the machine. That was in I found a relatively unheard of company, called Intel, that was involved with computers-on-a-chip, so I decided to send my resume. The company had a whole team of engineers doing the same things that I was doing by myself at GE, so we had a lot in common, and they made me an offer.
I don't know if it was my microprocessor experience that got me the job, or the fact that I was very involved with Volkswagen engines in those days and the hiring manager blew the exhaust valve on the number-three cylinder of his VW bus a week after he interviewed me.
SM: The state-of-the-art product at the time was the Intel But Zilog was eating Intel's lunch with a processor it had, called the Z The Z80 was an in every sense of the word, but it also filled in the 12 unused opcodes with some useful string-processing instructions. So it did more than the , and Zilog captured the 8-bit market. Intel wasn't too concerned because it was working on a new high-end processor called the which would change names a few times before finally coming to market as the , and it fully expected that chip to be the future of the company.
The schedules for the kept slipping uncontrollably, however, and management finally realized that they needed to come out with a midrange processor to counter the Zilog threat.
But nobody expected it to be anything more than a stopgap measure, because once the came out there would be no need for such a midrange solution. In the meantime I had just completed an evaluation of the processor design, and written a report on it. My report was critical and showed that the processor would be too slow. Because of my report, management decided that I would be the ideal person to design the architecture for the stopgap measure.
If management had any inkling that this architecture would live on through many generations and into today's Pentium processors, and be the instruction set executed by more instances of computers than any other in history by far, they never would have entrusted the task to a single person.
Instead it would have been designed by committee, and it would have come out much later than it did. The person I worked for, Terry Opdendyk, was in charge of the software group. He walked into my office one day and asked if I would design the instruction set for the new processor that Intel needed.
This was a complete break with tradition, because up until that time hardware people did all the architectural design, and they would put in whatever features they had space for on the chip. It didn't matter whether the feature was useful or not, as long as the chip real estate could support it. Now, for the first time, we were going to look at processor features from a software perspective. The question was not "What features do we have space for?
So there I was, a software person who would be chartered with what was normally considered a hardware task.
Although Terry remained my boss, for the work on the I would report to Bill Pohlman, who was the project manager for the new stopgap processor. SM: The only requirements that management gave me were to make it somehow compatible so Intel could tell customers that they could run their existing assembly-language programs and that it address at least KB of memory one of Intel's customers had an application that was exceeding the 64KB limit of the SM: The last revision of my evaluation was dated April 14, So we quickly started talking about the architecture rather than just the instruction set.
SM: When it started, it was just Bill Pohlman and myself. Bill was the project manager and I was the engineer. After I finished the first cut of the architecture specs, Bill brought on board a logic designer named Jim McKevitt. Jim and Bill were my primary points of contact in the hardware group. Many other people a chip designer and such were added to the project later, although I didn't interact with them directly. After I finished two revisions of the architecture specs, Terry enlisted Bruce Ravenel, a second software person I could bounce ideas off of, and together we kept refining the specs.
PCW: Describe the atmosphere and general feeling in your office during the creation of the SM: Company culture at Intel varied depending on the level you looked at. On the group level, things were great--the software team at Intel was top-notch, and we were all proud of what we were doing and how we were doing it. But at a higher level, the corporate culture often got in the way. Andy Grove was famous in those days for implementing a "late list.
At first we all laughed about it, because nothing was done with the list. And Opdendyk even advised us that if we could not get in by , we should simply not show up until after 9, when the list was taken down. Each segment register is bit. The segments are present in the memory and these registers hold the address of all the segments. These registers are as follows:. Code segment register : It is a bit register and holds the address of the instruction or program stored in the code segment of the memory.
Also, the IP in the block diagram is the instruction pointer which is a default register that is used by the processor in order to get the desired instruction. The IP contains the offset address of the next byte that is to be taken from the code segment. Stack segment register : The stack segment register provides the starting address of the stack segment in the memory.
Data segment register : It holds the address of the data segment. The data segment stores the data in the memory whose address is present in this bit register. Extra segment register : Here the starting address of the extra segment is present.
This register basically contains the address of the string data. It is to be noteworthy that the physical address of the instruction is achieved by combining the segment address with that of the offset address. As at the time of decoding and execution of the instruction in EU, the BIU fetches the sequential upcoming instructions and stores it in this queue. The size of this queue is 6-byte. This means at maximum a 6-byte instruction can be stored in this queue.
The queue exhibits FIFO behavior. The Execution Unit EU performs the decoding and execution of the instructions that are being fetched from the desired memory location. Like the timing and control unit in microprocessor, the control unit in microprocessor produces control signal after decoding the opcode to inform the general purpose register to release the value stored in it.
And it also signals the ALU to perform the desired operation. The arithmetic and logic unit carries out the logical tasks according to the signal generated by the CU. The result of the operation is stored in the desired register. Like in , here also the flag register holds the status of the result generated by the ALU.
It has several flags that show the different conditions of the result. In this section, we will discuss the other differences between and microprocessor using a comparison chart. Basically, it is called so because the ALU size is of 8-bit. It offers a data bus size of 8-bit with an address bus of bit.
Thus the permissible accessible memory space is 64KB. More specifically we can say that as one data byte is stored in one memory location, therefore overall 64 kilobytes of data can be stored by microprocessor. The arithmetic and logic unit of microprocessor is able to perform operations like add, subtract, compare, complement, increment, decrement, shift, AND, OR, X-OR. It is an accumulator based processor. This means that the data during operation reside in the accumulator and temporary registers.
Also, the output of the operation is stored in the accumulator and in accordance with the outcome generated, the flags get set and reset. It performs program execution in 3 stages, which are fetching , decoding and executing.
Firstly, fetching of instruction from the memory is done and then is stored in the instruction register. After that, the instruction is decoded by the decoder and the respective control signal is produced by the timing and control unit. According to the signal received the ALU performs the desired operation and stores the result in the accumulator and accordingly sets the flag register. The reason behind it being a bit microprocessor is the size of its ALU.
The data bus size in case of microprocessor is bit and that of the address bus is bit. Therefore, the permissible memory location offered by the microprocessor is 1 MB.
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